专利摘要:
An error count table is generated based on reading word lines of a flash memory device, the table storing an error count for each word line and voltage combination. respective reading level used to read the word lines. A plurality of offset word line groups are generated based on the error count table, each group associating a different read level shift voltage with a plurality of word line addresses. A storage device is configured to read the memory cells using a read level shift voltage of a generated offset word line group associated with a word line address of the memory cells to be read. After a predetermined point in a life cycle of a respective memory block, the table is regenerated and a plurality of offset word line groups are regenerated based on the regenerated error count table.
公开号:FR3033927A1
申请号:FR1652158
申请日:2016-03-15
公开日:2016-09-23
发明作者:Seyhan Karakulak；Anthony Dwayne Weathers；Richard David Barndt
申请人:HGST Netherlands BV；
IPC主号:

专利说明:

[0001] BACKGROUND OF THE INVENTION [0001] The present invention relates to information retrieval from flash memory devices such as electronic disks (SSDs). Low cost electronic disks (SSDs) are typically manufactured using multi-level cell (MLC) flash memory for increased data capacity, but MLC memory devices are sometimes less reliable than single-cell (SLC) flash memories . Consumer SSD manufacturers have moderated these problems by employing certain wear distribution algorithms. Even with the increased data capacity of MLCs, the use of MLCs in business applications becomes more expensive due to its disproportionately lower time in programming / erasure cycles (P / E) due to increased constraints (causing wear) necessary for reading, programming and erasing the flash memory, leads to a gradual degradation of the endurance. SUMMARY [0002] The invention relates to a method for recovering information stored in a flash memory. According to various aspects, the method may include reading a first example of word lines of a memory block, each of the first examples of word lines being associated with a word line identifier and being read multiple times in time. using different read level voltages to produce an error count for each word line and respective read level voltage combination, generating an error count table based on the counts of errors produced, the error count table indexing each error count produced by a corresponding word line identifier and a respective voltage of the different read level voltages used to produce the error count, and the configuration a storage device for performing read operations using selected read level voltages based on the error counts of the table error counts. Other aspects include corresponding systems, apparatus and computer program products for implementing the computer-implemented method. In various aspects, a data storage device may include a plurality of flash memory devices, each flash memory device including a plurality of memory blocks and a controller connected to the plurality of flash memory devices. The controller may be configured to read a first example of word lines of the flash memory device, each of the first word line examples being associated with a word line identifier and being read multiple times using level voltages. to generate an error count for each respective word line and voltage level combination, generate an error count table based on the error counts produced, the count table of errors 10 indexing each error count produced by a corresponding word line identifier and a respective one among the different read level voltages, and selecting read level voltages for future read operations based on on the error counts of the error count table. [0004] In various aspects, a method may include reading a first example of word lines of a flash memory device, each of the first examples of word lines being associated with a word line address and being read multiple times using different read level voltages to produce an error count for each respective word line and voltage level combination, generating an error count table by based on the error counts produced, the error count table indexing each error count produced by a corresponding word line address and respective one of the different read level voltages, the formation of a plurality of word line groups based on the error count table, each group associating a respective one of the different read level voltages to a plurality of addresses of the word line, and the configuration of a storage device for reading the memory cells using a read level voltage of a generated word line group corresponding to a word line address of the memory cells. memory to read. It is understood that other configurations of the present invention will become readily apparent from the following description to those skilled in the art, wherein various configurations of the present invention are indicated and described by way of illustration. As will be appreciated, the present invention is capable of adopting different and different configurations and its many details may be modified under various other aspects, all without departing from the scope of the present invention. Therefore, the drawings and the detailed description are to be considered illustrative and not restrictive. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an exemplary diagram of four possible cell threshold voltage (VT) distributions and associated program read levels for a group of memory cells in a cell-based flash memory. Multilevel (MLC). Figure 2A shows an example of probability determination for a low-order bit page (LSB) using three read levels. Figure 2B shows an exemplary probability determination for a high-order bit (MSB) page of a MLC flash memory using three read levels. [0009] Figure 3 shows an example of optimal reading level voltage variations for multiple word lines of a memory block. Figure 4 shows an exemplary error count table for an exemplary range of read level offset values for multiple word lines. Figures 5A to 5C show graphs of examples of optimal reading level offsets for memory blocks subjected to cycles. Figure 6 is a block diagram of an exemplary algorithm for generating shifted word line groups. FIG. 7 represents a process diagram of a first example of a process for generating groups of offset word lines. Figure 8 shows a flow diagram of a second exemplary process of generating offset word line groups. FIG. 9 represents an example of a flash memory channel modeled as a discrete-memory-less channel (DMC) with binary inputs and K-ary outputs. Figures 10A to 10C show an example of linear interpolation graphs for calibrating examples of read levels and / or read level offsets. Figures 10D-10F show an example of linear interpolation graphs for recalibrating examples of read levels and / or read level offsets. Figures 11A and 11B show examples of modes of optimizing the reading level. Figure 12 shows a flow diagram of an exemplary process of calibrating the read levels for reading a plurality of memory cells in a storage device. Fig. 13 shows a flow diagram of an exemplary read level calibration process for data recovery. Fig. 14 shows a flow diagram of an exemplary regeneration process of a plurality of optimal offset word line groups based on the regeneration and reindexing of an error count table. Figure 15 is a block diagram showing the components of an exemplary data storage system. DETAILED DESCRIPTION [0023] The detailed description set forth below is intended to be a description of various configurations of the present invention and is not intended to represent only configurations in which the present invention may be practiced. The accompanying drawings are incorporated herein and form an integral part of the detailed description. The detailed description includes specific details to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can be implemented without these specific details. In some circumstances, structures and components are represented in block form to avoid masking the concepts of the present invention. Identical components are provided with identical reference numerals for ease of understanding. In a flash memory device, for example with a NAND architecture, the memory cells are grouped in strings, each string being composed of a set of transistors connected in series between a drain selection transistor (connected to a respective bit line of a memory block) a source selection transistor (connected to a reference voltage distribution line). Each memory cell contains a floating trigger MOS transistor. When programming a memory cell, electrons are injected into the floating gate, for example by means of the Fowler-Nordheim tunneling effect (F-N) and / or hot electron injection. The nonvolatile nature of the cell is due to the electrons held inside the floating trigger. The bits are stored by trapping the load on the floating trigger (an electrically isolated conductor) which stores a logic value defined by its threshold voltage (the voltage required to drive the cell), which is proportional to the stored electrical charge. When a memory cell is erased, the electrons in the floating gate of the cell are torn off by tunneling (a tunnel current) of the floating gate to, for example, the source and / or the substrate. When a flash memory is cycled (i.e. programmed and erased repeatedly), its physical qualities change. The repeated implantation and removal of electrons on the floating gate, for example during the programming and erasure operations respectively, has the effect that some excess electrons are captured in the device. Similarly, when one or more cells are programmed, the neighboring cells may experience unexpected and unwanted charge injection to their floating gates, resulting in corruption of the data stored therein. For example, electrons can leak into neighboring cells after prolonged stress due to the voltages at the triggers of neighboring cells. The threshold voltages of these memory cells may possibly take different values (higher or lower) than the expected values, which causes errors when reading the data. The damage caused generally becomes a function of the intensity (e.g. voltage) and duration of the field; which is to say that programming the flash memory at high threshold voltage conditions increases the damage rate resulting from both the programming and erasure processes, because it requires fields applied for a longer duration and or at a higher level. Adding a sufficient number of electrons, for example, can change a cell from an erased state to a programmed state. In various embodiments, the memory cells are arranged on a wafer in a matrix of columns (bit lines) and lines (word lines). The address of a memory cell represents the intersection of a bit line and a word line corresponding to (eg, indexing) the memory cell. A flash memory may further be composed of blocks, each block being divided into pages. In some MLC memory embodiments, each cell line of the flash memory is composed of 2 pages: an LSB page and an MSB page. If a block has 128 pages, then it can have 64 rows of cells, each line consisting of two pages. Each line may exhibit different behavior because when cells are physically together in a chip, they are subject to variations in voltages and resistances as well as other characteristics as part of the manufacturing process. In NAND architecture, it has been found that the problem of degradation is particularly problematic because each transistor in the string of cells read (for example at a bit line) receives a high voltage stress, even if a number less than all the cells of this chain (for example at a location in the bit line corresponding to a designated word line) can be read at any time. Due to the degradation, when programmed, the cells of certain lines (word lines) are further from their expected values (for example an expected voltage measured at a corresponding bit line) than from other. It has been observed that these variations can be associated with individual word lines. Therefore, the technology according to the invention characterizes these variations as a measurable value and provides a mechanism to compensate for variations in performance. If it is found, for example, that the cell voltages in a word line are shifted (for example as a result of a characterization process), a bias (eg an offset voltage) can then be introduced during the following programming or reading operation to correct the programmed voltage or read value. The non-linearity of the actual programming values between the cells in the different word lines can thus be reduced, which in turn reduces errors when reading the cells. The same bias, however, is not necessarily suitable for a uniform correction of errors related to reading through a particular block or chip.
[0002] In addition, the storage of polarization values for each word line or block can quickly consume memory useful for storage and can become unmanageable and / or affect performance by requiring many consultations to apply the correct bias to each operation. reading. Therefore, the technology according to the invention provides a mechanism for determining and associating the polarization values with groups of word lines, the bias values being optimized for the lowest possible reading error rate for reading. lines of words within a group. The technology according to the invention further provides a mechanism for optimizing the polarization values over the lifetime of the memory cells. Polarization values can thus be efficiently stored and recalled, and corrected if necessary, thus improving the reliability and endurance of the overall architecture of the flash memory cell, making the flash memory suitable for business applications. FIG. 1 is an example of a diagram of four possible cell threshold voltage (VT) distributions (401, 410, 420 and 430) and associated program reading levels (thresholds LO, Li and L2) for a group of memory cells in a multi-level cell (MLC) flash memory according to one aspect of the technology of the invention. MLC NAND flash memory provides more than one bit per cell by choosing between multiple levels of electrical charge (read level) to be applied to the floating trigger of its cells to obtain multiple conductivity states, each occurring at a different voltage threshold VT. As illustrated in FIG. 1, a NAND MLC cell is capable of storing one of four (charge level) states per cell, producing two logical bits of information per cell: the most significant bit (MSB) and the low weight (LSB). These two bits can constitute the MSB and LSB pages of a memory block. Figure 1 shows the probability density distribution curves 400 for a group of memory cells (for example in a block) programmed at data levels LO, Li, L2 and L3. The distributions 401, 410, 420, and 430 correspond to the probability density distribution curves respectively for the LO, L1, L2, and L3 data levels. Each level of data is separated by a corresponding threshold voltage level. In the example shown, the threshold voltage levels are identified as the threshold LO, the threshold Li and the threshold L2. Threshold voltage levels are used by a threshold detector (e.g., within the flash memory) as "read levels" to determine, for example, whether to read a read signal considering that it is in the distribution 401, 410, 420 or 430. The four cell distributions 401, 410, 420 and 430 of Figure 1 can be obtained from laboratory data. To ensure that all cells in a distribution will conduct, a reading level voltage greater than the distribution is applied. In the various examples described here, a first read level RL1 corresponds to the threshold voltage LO, a second read level RL2 corresponds to the threshold voltage Li and a third read level RL3 corresponds to the threshold voltage L2. In this regard, the voltage RL1 will cause the cells in the LO distribution to be driven, the RL2 voltage will cause the cells in the Li distribution to be driven, the RL3 voltage will bring the cells into the L2 distribution to drive, etc. When only four states are available, as shown in Figure 1, the voltage RL3 will not bring any cells into the L3 distribution to drive. In some embodiments, this will produce a binary x0 in the LSB for these cells. For N distributions, there will generally be N-1 levels of reading. In the example shown, there are four distributions (states) and three read levels. However, it is understood that there may be eight, sixteen or even more distributions without departing from the scope of the technology according to the invention. FIG. 2A shows an exemplary probability determination for an LSB page using three reading levels RL1, RL2 and RL3, in accordance with an aspect of the technology according to the invention. In the example shown, a first read level 202 ("RL2") is used in a first read of an LSB page to determine the putative programming levels for the memory cells of the LSB page. Several virtual reads are initiated to determine a probability that the memory cells have actually been programmed to the observed putative programming levels. In the example shown, the memory cells are read using a second reading level 204 less than the first reading level 202 and a third reading level 206 greater than the first reading level 202. A first The program BI contains one or more cells having a programmed value between the first reading level 202 and the second reading level 204, and a second program region 82 includes one or more cells having a value programmed between the first reading level. 202 and the third reading level 206. The different regions 5 between the reading levels can here be referred to as "bins". In various aspects, a confidence value can be calculated for each bin based on the number of memory cells in the bin compared to one or more other bins. A confidence value can be determined for a bin based on an area 208 below the bin distribution curve. The confidence value is then assigned to each memory cell in the corresponding bin. As will be described later, the confidence values may include log likelihood ratios. Figure 2B shows an example of determining the probability for an MSB page of the MLC flash memory using three read levels RL1, RL2 and RL3. In accordance with aspects of the technology of the invention, an initial read level 202 may be applied to one or more memory cells to obtain an LSB value for each memory cell. In the example shown, the read level 202 is chosen as the state transition location between the distributions of the coded bit 1 and the coded bit 0 in order to reduce to a minimum an expected bit error rate (BER). Reading levels chosen to minimize BER are called optimal reading levels. Based on the value of the LSB, a first read level 202 may be determined for reading a putative program level for the MSB. Once the first reading level 202 is determined and the program level read, multiple subsequent readings can be initiated to determine a probability that the memory cell was actually programmed to the observed putative program level. Therefore, each cell may be associated with a program region (bin) ao, ai, a29, a3, 124, a5, and ci6 corresponding to the level at which it has been found that the cell is driving or not driving when one or many of the following readings are applied. [0036] Figure 3 shows an example of optimal reading level voltage variations for multiple word lines of a memory block, in accordance with aspects of the technology of the invention. A memory block can include up to 64 word lines (or more). Laboratory results indicated that optimal reading levels (eg RL1, RL2 or RL3) may vary from one word line to another.
[0003] In the example shown, three reading levels RL1, RL2 and RL3 are optimally set to their respective values for reading the memory cells in the probability density distribution curves corresponding to the LO, Li, data levels. L2 and L3. However, it turns out that the values or voltages of these optimal reading levels change with respect to each line of words. The optimal reading levels for the word line 1, for example, are shifted to the right, having a slightly increased value, while the word line 64 is shifted to the left by having a slightly reduced value. As will be described later, each of these voltage offsets for each read level can be represented as bias values, or read level offsets, with respect to a corresponding primary read level voltage. FIG. 4 shows an exemplary error count table 400 for an exemplary range of read level offset values for multiple word lines, in accordance with various aspects of the technology of the invention. As explained above, the optimal reading level used to read a particular state of the memory cell may vary from word line to line, illustrating that each word line may have a unique set of words. characteristics with respect to each other. The variations of the optimal reading levels between the word lines can be represented by modifying a primary reading level of a particular polarization, also referred to herein as "reading level shift". The read level shift may be different for each word line and / or each block and / or each memory chip. In this regard, multiple offsets may be applied: one for each word line, one for each block and / or one for each memory chip.
[0004] 100381 Each row of table 400 is representative of a different word line, while each column is representative of a different read level offset value. Each word line of a block can be represented in the table. The error counts enumerated in the sample table are the error counts produced when reading the word line corresponding to the corresponding offset value. Error counts can be indexed by word line and read level offset value. The read level offset values are represented as "tops" relative to a primary read level voltage. In some embodiments, every second peak may be the equivalent of 25 mV. In addition, there may be a different table for each read level voltage. The illustrated table may be for RL1, for example, 3033927 11 while a different table provides the error counts for reading the same word lines with RL2 and a different table provides the error counts for reading the same lines of words with RL3. The table can be generated initially based on data obtained in the laboratory. In at least one example, the error count table can be generated based on the reading of the word lines of a memory block, each word line being read multiple using a reading level voltage chosen. modified for each reading by a different offset voltage. Therefore, an error count is generated for each offset voltage and the table is generated for indexing the error counts per word line and respective offset voltages. Figures 5A to 5C show graphs of examples of optimal reading level offsets for memory blocks subjected to cycles, according to various aspects of the technology according to the invention. As explained above, the memory cells may experience some degradation when subjected to cycles.
[0005] Therefore, LO, Li, L2, and / or L3 distributions may drift or deviate from expected values, and new optimal reading levels are required to read the cells at their new values with minimal errors. In the illustrated examples, the optimal read level offset values are plotted for the 128 word lines (0-127) of a memory block for the primary read levels RL1, RL2, and RL3. Figure 5A is representative of MSB page reading examples using RL1, and shows how the read level shift values can vary between 18 and 12 tops before settling at 14 tops for word line numbers. the highest. Figure 5B is representative of the examples of reading LSB pages using RL2. Figure 5B shows how a larger offset (ie, 18 tops) is required at the lowest wordline numbers (e.g. at the beginning of a block) than at the word line numbers. the highest (for example at the end of a block). The read level offset to be applied to RL2 is generally considered to have a decreasing value, from 18 tops for the word line 0, to 10 tops for the word line 120, and finally to 4 tops at the word line 127. Figure 5C follows a similar model. Figure 6 is a block diagram of an exemplary algorithm for generating offset word line groups according to various aspects of the technology of the invention. Algorithm 602 can be implemented in the form of a computer program (e.g., instructions executed on a computer processing device), electronic hardware, and combinations of both. Storing the offset values necessary to provide the optimum reading levels for reading the memory cells in each of the 128 word lines, for example, using three (or more) different read levels, would occupy a large memory space. . Therefore, the technology according to the invention implements a read level profiling algorithm 602 which reduces the amount of offset values (or read levels) that need to be stored while producing a rate reduction. of near-optimal bit errors in memory read operations. The read level profiling algorithms 602 reduce the number of stored read level offsets without degrading the bit error rates produced by the corresponding read operations which could increase hardware or software decode defects. The example of read level grouping algorithm 602 uses the initial boundary conditions as inputs, for example in the form of an initial word line division for a block and the count table of 400 errors described above. Each division of word lines defined by the boundary conditions forms a set of candidate word (input) line groups, each consisting of consecutive word line addresses. The initial boundary conditions may designate, for example, four candidate groups, with group 1 as wordlines 0-31, group 2 as wordlines 32-63, group 3 as lines of words 64-95 and group 4 as word lines 96-127. These candidate groups define the initial boundary conditions that will be used by algorithm 600 to analyze error rates and eventually generate the optimal boundary conditions to form optimal (output) offset word line groups to be used in applications. read operations during the operation of a storage device. The exemplary algorithm 602 uses the table 400 and the initial boundary conditions and outputs groups of optimal offset word lines. Each optimally offset wordline group outputted by algorithm 602 contains a consecutive portion of the total number of wordlines inputted as part of the initial conditions (e.g., 128 wordlines). The boundaries of the optimal offset word line groups outputted by the algorithm 602 may or may not be identical to the initial boundary conditions, and in many cases they will be different. Each optimal offset line group contains consecutive group word lines matched with a corresponding optimal offset voltage for the group. Groups can be sorted consecutively for their 5-word lines. Each pairing of each group of word lines offset optimal to each respective optimal offset voltage is automatically selected by the algorithm for a global error count as low as possible for the reading of the word lines in each of the groups. off-line words and groups as a whole.
[0006] The set of optimal offset word line groups generated by the algorithm 400 is generally generated, at least in part, based on the iterative indexing of the table 400 based on the location of the line of words and offset values for each initial set of word line groups to determine a better adjusted or normalized error count for each output group. Therefore, the read level grouping algorithm 602 outputs optimal offset word line groups (e.g., as limits for each group) and optimal reading level offsets (or read levels). ) for each group with the lowest bit error rate degradation, for example based on input table 400. Figure 7 shows a flow diagram of a first example of process 700 of FIG. generation of offset word line groups according to various aspects of the technology according to the invention. For the purpose of explanation, the various blocks of the example process 700 are written here with reference to the components and / or processes described herein. The one or more blocks of the process 700 may be implemented, for example, by one or more processors comprising, for example, the controller 1501 of FIG. 15 or one or more components or processors of the controller 1501. In certain modes one or more of the blocks may be implemented separately from the other blocks and by one or more different processors or controllers. Still for the purpose of explanation, the blocks of the example process 700 are described as appearing in series or in a linear fashion. Multiple blocks of the example process 700 may, however, appear in parallel. Further, the blocks of the process example 700 need not be executed in the indicated order and / or execution of one or more of the blocks of the example process 700. is not necessary. According to various embodiments, the blocks of the process 700 are implemented by the read level grouping algorithm 602. In this respect, the blocks 5 of the process 700, or a subset thereof, ci, can be executed for each possible reading level used in a memory device. The blocks of the process 700 may, for example, be executed to generate optimal offset word line groups for RL1, RL2 and RL3 based on the table 400 and the input boundary conditions. In various aspects, groups of offset word lines of different sizes and / or with different offset value matches can be generated for each different read level. In addition, the blocks of the process 700 can be executed to generate different groups for different blocks and / or chips. The process 700 can be implemented during the configuration of a storage device, before or during its use. [0047] In general, for each initial boundary condition, the process 700 performs a number of iterative steps to automatically select the optimal group boundaries and corresponding optimal read level offsets for each group that has the highest number of iterations. a small increase in the overall bit error rate compared to the optimal bit error rate, as determined by a corresponding input table 400. For a given number of candidate groups defined by the boundary conditions, the algorithm 600 can select two consecutive groups k and k + 1 and, starting from the first element of the first group to the last element of the second group, consider all pairs of consecutive divisions possible. In the illustrated example, the word lines of a block are divided into candidate groups (702). In an example in which 128 word lines are used, the block can be divided into four candidate groups, with group 1 as word lines 0-15, group 2 as word lines 16-31, group 3 as wordlines 32-63, group 4 as wordlines 64-79, etc. As previously described, the division of groups can be represented as group boundaries. Process 600 then selects a set of consecutive candidate groups (704). Groups 1 and 2 can be selected, for example, thus forming a set of wordlines between 0 and 31. Permutations of multiple consecutive subgroups of the set are envisioned (706). Permutations of two subgroups are contemplated in various examples herein, however, a larger number of subgroups may be contemplated. Since, in the example shown, the subgroups are consecutive and the word lines within the group are consecutive, the maximum number of permutations for n word lines will be n1 permutations. The permutations of an example of a set of word lines covering 0-31 may include {[0, 1-31], [0-1, 2-31], [0-3, 4-31]. . . [0-30, 31] 1. [0049] Process example 700 is represented as a min-average algorithm. That is, for each possible permutation, the average error count is calculated based on a corresponding error table and then the subgroups within the permutations are compared to select those with the smallest count. errors. In this regard, the error counts for each subgroup are calculated using all the available reading level offsets based on the error count table 400, and the reading levels that offer the smallest counts. errors for each permutation are determined. In the example shown, the process 700 starts (or selects) a first permutation (708) and then, for each subgroup within the permutation (710), searches for the total error count corresponding to the sub-group. group for each offset value shown in input table 400 (712). The total error count can be found, for example, by indexing the table 400 to a first offset value represented in the table 400 and each word line within a first (i = 1) subgroup to determine the error counts for each word line within the subgroup, and then adding up the determined error counts. The total error counts for the other offset values represented by the table 400 are determined in the same manner, and the sums obtained from the error counts are compared in order to identify the offset value having the smallest count. errors for the subgroup. The identified offset value is then selected and associated with the subgroup (714). The same process is applied to the next subgroup of the permutation. The preceding process is repeated (716), restarting at block 708, until an offset value is associated with each subgroup of each permutation, each subgroup also being associated with a count of each. total errors corresponding to the associated offset value. Table 1, below, contains examples of shift associations for three permutations of two subgroups.
[0007] 3033927 16 Permutation Offset of first subgroup Offset of second subgroup TEC of first subgroup TEC of second subgroup 0, 1-31 16 14 28640 16254321 0-1, 2-31 18 16 63012 16222110 0-2 Table 3 Example of Offset Associations for Selected Permutations [0051] Once offset values are associated In each subgroup of each permutation, process 700 selects a permutation having the smallest total error count (718). The smallest total error count may be the total error count of the two subgroups within the permutation, or the first or second subgroup, depending on the implementation of the algorithm used. In various examples, the cumulative total error count between all the word lines (of the two subgroups) is used to compare the permutations. Process 700 continues by selecting the first subgroup and its corresponding offset of the selected permutation as the optimum pair (720). The process 700 continues by selecting a third candidate group and repeats the previous steps with the second subgroup and the third candidate group. In the illustrated example, process 700 determines whether there are more candidate entry groups (722). If there is a next candidate group (for example the word lines 32-47 in the example above), the second subgroup of the permutation identified in block 718 is then selected and put back into factor in the algorithm. with the next candidate group (724). In the example above, the first subgroup site contains the word line boundaries of 0-22 generated based on first and second candidate groups (having the word line boundaries 0-31), then the second subgroup having the word lines 23-31 will be used in the next set of candidate groups together with the next next candidate group entry in the algorithm. Therefore, in the above example, the next set of candidate groups would include a candidate group having the word lines 23-31 and a candidate group having the word lines 32-47.
[0008] If a next candidate group does not exist, then the algorithm may select the second subgroup and its corresponding offset of the permutation identified in block 718 as the final optimal pair (726). The process 700 may be repeated until the group boundaries obtained do not change from one iteration to the next, or until a number of iterations have been reached. Each iteration may be performed using the same initial boundary conditions, output boundary conditions produced at the end of block 726, or new / different boundary conditions. Randomization can also be introduced in process 700. It is possible, for example, to generate permutations that contain subgroups that are not in any particular order. A first subgroup 10 may include the word lines 13-31 and a second subgroup may include the word lines 0-12. Although the exemplary process 700 is represented in the form of a min-mean algorithm, other types of algorithms can be implemented. A minmax algorithm can be implemented, for example. Thus, the block 712 can be modified so that for each subgroup within the permutation (710), look for the maximum error count of all the word lines in the subgroup for each offset value. (712). The maximum error count can be found, for example, by indexing the table 400 according to a first offset value and comparing the error count indexed by the first offset value with each word line in the sub-value. group (e.g., the word lines 0, 1, 2 and 3 in the first permutation subgroup {[0-3], [4-31]}). The maximum error counts found for each of the offset values are then compared and the offset value corresponding to the minimum of all maximum error counts is then selected and associated with the subgroup (714). The same process can be applied to the next subgroup of the permutation. An advantage of the process 700 implementing a min-max algorithm includes maintaining errors below a maximum capacity of the error correction encoding used by the storage device to correct errors. In some aspects, the technology according to the invention may include the implementation of blocks or steps different from those developed above in connection with the example of process 700. At the initial limits and the table 400, the process 700 outputs bounds for optimal offset word line groups, including optimal reading levels for each group offering, for example, the least degradation in the rate of change. binary errors for each word line in each group relative to the optimal values in the table 400. [0056] FIG. 8 represents a process diagram of a second example of a process 800 for generating offset word line groups, in accordance with FIG. to various aspects of the technology according to the invention. For the sake of explanation, the various blocks of the example process 800 are described with reference to the components and / or processes described herein. The one or more blocks of the process 800 may be implemented, for example, by one or more processors including, for example, the flash memory controller 1501 of Figure 15 or one or more components or processors of the controller 1501.
[0009] In some embodiments, one or more of the blocks may be implemented separately from the other blocks and by one or more different processors or controllers. Still for the sake of explanation, the blocks of the process example 800 are described as appearing in series or in a linear fashion. Multiple blocks of the example process 800 may, however, appear in parallel. Further, it is not necessary that the blocks of the example process 800 be executed in the indicated order and / or the execution of one or more of the blocks of the process example 800 n '. is not necessary. According to various embodiments, the blocks of the process 800 correspond to, or complete, one or more of the blocks of the process 700. In this regard, a portion of the blocks of the process 800 may be executed by the algorithm 600 The blocks of process 800, or a subset thereof, may be executed for each possible read level used in a memory device. The blocks of the process 800 may be executed, for example, to generate optimal offset word line groups for RL1, RL2 and RL3 based on the table 400 and the input boundary conditions.
[0010] In various aspects, groups of offset word lines of different sizes and / or having different offset value matches can be generated for each different reading level. In addition, the blocks of the process 800 can be executed to generate different groups for different blocks and / or chips. The process 800 may be implemented during the configuration of a storage device, before or during its use. In the illustrated example, a system according to the technology of the invention provides a read level voltage sufficient to read a majority of memory cells that are programmed at a predetermined programming level (802). In some embodiments, each memory cell is a multilevel nonvolatile memory cell configured to be programmed at one of four programming levels. The first and fourth programming levels, for example, can be associated with first bit values (for example representative of a 0 or a binary 1 of a most significant bit) and the second and third levels of programming can be associated with the second bit values (for example representative of a 0 or a bit 1 of a least significant bit). As previously described, when a voltage is applied to a memory cell at a particular read level (e.g. RL1, RL2, RL3) corresponding to the program level of the cell, the cell will drive indicating the program level. The system divides a plurality of memory word lines into a plurality of optimal word line groups, each word line group being associated with one of a plurality of normalized reading level offsets (804). Each of the optimal word line groups consists of word lines sorted in the consecutive order of a memory block, the word lines of a first of the groups preceding here the word lines of a second of the groups. . In this regard, each offset is normalized for a better error rate resulting from using the offset with the read level voltage to read the word lines of a corresponding word line group. In some embodiments, dividing the plurality of word lines into the optimal word line groups includes selecting the respective permutations of the consecutive word line subgroups from a predetermined set of candidate groups of words. lines of words based on a minimum total error count associated with the respective permutations (eg blocks 702-706 of Figure 7). Thus, each of consecutive word line subgroups is associated with a read level offset corresponding to a minimum of the error counts associated with a plurality of possible read level offsets. Referring to Figure 7 as an example, the first and second groups of consecutive word lines may be selected from the predetermined set of candidate word line groups (704). As previously described, the groups of candidate word lines may be based on the initial boundary conditions. A plurality of subgroup permutations can then be performed for the first and second consecutive groups of selected word lines (706), each subgroup permutation comprising multiple subgroups of consecutive word lines of 3033927 20 words covering the first and second groups of consecutive word lines. For each sub-group of word lines of a respective subgroup switching, a respective read level shift can be selected from the possible read level offsets, so that when used with the voltage In order to read the word lines in the sub-group of word lines, the respective reading level offset generates the smallest error count for the word line subgroup (714). The plurality of subgroup permutations having the lowest total error count for the consecutive word line subgroups in the subgroup permutation can be selected (718). Therefore, the plurality of word line groups may be based at least in part on one or more read level offsets corresponding to the plurality of selected subgroup permutations. In some embodiments, dividing the plurality of word lines into the plurality of word line groups includes selecting the respective permutations of consecutive word line subgroups from within a set of word lines. predetermined number of candidate word line groups based on a minimum of maximum error counts associated with the respective permutations, each of consecutive word line subgroups being associated with a read level offset corresponding to a minimum of maximum error counts associated with a plurality of possible read level offsets. By way of example, for each subgroup of word lines, the system can determine a maximum error count generated for a word line in the word line subgroup when each of the read level offsets. possible is used with the read level voltage to read the word lines of the subgroup of word lines. A reading level offset corresponding to the minimum of the maximum numbers determined can then be selected from the plurality of possible read level offsets. For each subgroup permutation, a maximum error count of the selected read level offsets corresponding to subgroups of word lines of the subgroup permutation is determined. The subgroup permutation having the minimum of the maximum error counts determined for the subgroup permutation is then selected (see for example 718). In one or more of the above implementations, each consecutive word line subgroup of a respective permutation can be generated based on an interleaving of consecutive word lines within the set. predetermined number of groups of candidate word lines. Interlacing can be used to introduce randomization. A first subgroup of word lines in a subgroup permutation may contain, for example, the word lines 14-31, followed by a second subgroup which contains the word lines 0-13. In a subgroup permutation which contains three subgroups, a first subgroup of word lines of the permutation may contain the word lines 4-6, a second subgroup of word lines of the permutation may contain the word lines 0-3 and a third subgroup of word lines of the permutation can contain the word lines 7-32. In addition, each respective normalized reading level shift can be generated (for example using any of the above embodiments) based on the indexing of a rate table. errors, each error rate in the table being indexed based on a respective read level offset and a respective word line. Thus, the table may be indexed by a plurality of consecutive word lines in order to identify the corresponding reading level offsets having the lowest error rate for each consecutive word line and to determine a group of rows of words. consecutive words which, when associated with a unique identified offset, have a possible minimum error rate for the consecutive word line group. Once the word line groups have been generated, the plurality of normalized read level offsets are associated with their respective optimal word line and stock groups to be used in reading the memory cells for a period of time. the operation of the storage device (806). In this regard, the foregoing process automatically selects the optimum optimum group boundaries and reading level offsets for each group that has the smallest increase in overall bit error rate compared to the optimal bit error rate. Many of the above described features of the 700 and 800 process examples as well as related features and applications can be implemented in the form of software processes that are specified as a set of instructions. recorded on a computer-readable storage medium 30 (also known as a computer-readable medium). When these instructions are executed by one or more processing units (for example one or more processors, processor cores, or other processing units), they cause the processing units to perform the actions indicated in the instructions. Examples of computer readable media include, but are not limited to, CD-ROMs, flash drives, RAMs, hard drives, EPROMs, and the like. Computer readable media does not include carrier waves or electronic signals transmitted wirelessly or over wired connections. In low density parity (LDPC) applications, a log likelihood ratio (LLR) may include the logarithm of a ratio of the probability that a bit is "0" or "0". "1". The LLR can cover a predetermined range. In some embodiments, for example, an LLR may cover the range of -255 to +255. An LLR may generally indicate that a read signal from the memory cell is likely to be a 0 bit, and a negative LLR may generally indicate that a read signal from the memory cell is likely a 1-bit. be associated with the value of the bit read from the memory cell. A bit associated with a LLR equal to 5 may be a binary zero with more likelihood than a bit which is assigned an LLR equal to 1. A bit which is assigned an LLR equal to 0 may be a 0 or a binary 1 with the same likelihood. If, at a certain reading level, a bit at 0 is read from a memory cell, a positive LLR can then be assigned. If a 1 bit is read, then a negative value can be assigned. In a multilevel memory cell comprising two bits, there are multiple potential levels of cell distribution (eg LO, Li, L2 and L3). The distinction of a binary 1 and a binary 0 in a reading of an MSB may require determinations among multiple reading level limits. In the example of FIG. 1, the distinction between 0 and a 1 requires determining whether the cell leads inside the two distributions of the center Li and L2 (for example for a binary Ox), or in the extreme distributions LO and L3 (for example for a binary lx). Therefore, multiple read levels may be involved (eg, RLO and RL2) to make this determination. FIG. 9 represents an example of a flash memory channel 900 modeled as a channel without discrete memory (DMC) with binary inputs and K-ary outputs, in accordance with aspects of the technology according to FIG. invention. In this example, the K-ary outputs correspond to the K cell program regions (trays) that can be identified with multiple reads. The 900 channel model provides a log likelihood (LLR) definition for a 3033927. Using this model, the LLR can be defined as follows: (1) LLR, = log p (s, = 01 ri) log = 0) p (s, = 0) 1 p (ri) p (s,. = In some embodiments, it can be assumed that all inputs have the same probability; in this case, the expression of equation (1) becomes: (2) LLR, = logp, fr1s "= 0) p (ri I s, = 1) [0070] Referring to Figure 2A, if K = 2 for a read LSB page, the K regions are designated as r, E {oe0,}, the LLR for region ai of Figure 2A given by: LLR (ai) = log s, 0) it (3) = a1 si = 1) [0071] Referring to FIG. 2B, in the case where K = 7 for an MSB page read, the regions can be designated as: (4) ie {ero, The reading level can be adjusted before each of the N readings A conversion table can be used to determine the number of read levels and read level values based on the readings. on the number of bins to be used in determining the LLR values for the memory cells A flash memory device may be instructed to read the LSB or MSB page using the stored read levels As previously described, to create the bins, a first read level is used to determine a putative value of the cells and then multiple reads (e.g., a read run) are made to determine the associated LLR values. In some aspects, the read levels are determined by varying the first read level of a predetermined (e.g., stored) offset associated with a respective tray. This offset may be different from the offsets that are determined by the technology according to the invention. invention. The transitions in the read data are analyzed to determine which region contains the voltage threshold (VT) of each memory cell. Therefore, the first reading level can be stored (for example temporarily) and a region can be determined based on a binary value (eg, positive or negative) read from the memory cell, and then the differences between the first one. reading level and subsequent reading levels initiated by a memory controller. Reading levels may or may not be changed in a predetermined order. If the playback levels are changed in a prescribed order, only the previous playback level can be stored and the program region of the cell determined at each subsequent reading. If all 10 readings are made (for example immediately), a conversion table can be used to determine the trays based on the received binary values. Once determined, a bin number can be determined for each program region of the cell. The LLR assigned to the bin can be applied to all cells inside the bin. For each memory cell, the bin number is mapped to a value of LLR in a conversion table. In accordance with the above, for a primary reading level (for example RL1, RL2 orRL3), the number of trays will be equal to the number of readings plus one. Therefore, a table generated for the LLR values can include 8 columns corresponding to the 8 bins. In this example, an MSB page may comprise two lines, as shown in Table 2: 0 1 2 3 4 5 6 7 RL1 -255 -114 -133 -116 -78 -38 5 117 RL3 174 154 127 91 50 7 -38 -133 Table 2 [0075] The location of the primary reading level from Table 2 is between Tray 3 and Tray 4. A generated table for the LSB page may require only one line, such as shown in Table 3: 0 1 2 3 4 5 6 7 RL2 -255 -199 -163 -119 -70 -23 24 110 25 Table 3 3033927 As described previously, offsets (or polarization values) can be be implemented in association with the primary reading levels (eg RL1, RL2, RL3) in order to obtain an optimal reading level having a low bit error rate. The offset values can be defined globally, for example for a chip or a block, or individually for each word line. Each line of words may have different and / or unique characteristics that cause each line of words to present more or less errors during the reading operations. Therefore, in order to obtain the best error rate - the minimum error rate - the optimal reading level has to be determined. In some aspects, the optimal reading levels for a word line can be determined by data obtained in the laboratory. In various examples described here, the word line can be read at different offsets and the error count for each read placed in a table for later comparison. Although such laboratory data may be useful for a portion of the memory life cycle, the characteristics of the memory cells change over time and the data may not be very useful for obtaining the best rate of memory. errors after a given period of the memory cell lifecycle. Different tables 400, for example, can be stored in the memory for each reading level (for example RL1, RL2 or RL3) and for multiple different periods in the expected time of view of the memory, so that a device can achieve a near-optimal bit error rate throughout its expected lifetime. The data obtained in the laboratory may, however, not be applicable to each chip, each block or even to each form of degradation that can be experienced by the individual word lines or memory cells during the lifetime of the device. Therefore, the technology according to the invention provides a dynamic calibration mechanism (for example at the time of execution) of the reading levels by estimating optimal reading levels and / or offsets during operation of the memory device. Figures 10A to 10C show an example of linear interpolation graphs for calibrating examples of read levels and / or read level offsets, in accordance with various aspects of the technology of the invention. The graphs are representative of how an algorithm of the technology according to the invention determines a new calibrated offset for read operations. Referring to Tables 2 and 3 above, each graph plots a calculated LLR value with respect to the predetermined offset values associated with each bin. Therefore, the X axis represents a range of negative and positive offset values with respect to a non-calibrated zero offset 902. In the example shown, the uncalibrated offset 1002 (marked "0") corresponds to the read level " corresponding "central" (e.g. RL1, RL2 or RL3) used to initially determine the programmed level of a memory cell, before it is read back by the "extra" read levels used to generate the bins. Each tray covers 6 tops on the X axis, in accordance with a fixed amount. In the example shown, the offsets are uniformly spaced 6 tops. The offsets 0 to +6 on the X axis correspond to the tray 4, the offsets +7 to +12 correspond to the tray 5, the offsets +13 to +18 correspond to the tray 6 and the offsets +19 to +24 correspond to the tray 7. Similarly, offsets 0 to -6 on the X axis correspond to tray 3, offsets -7 to -12 correspond to tray 2, offsets -13 to -18 correspond to tray 2, and offsets -19 at -24 corresponds to tray 0. The corresponding LLR values placed in the trays are respectively plotted at the offset values -21, -15, 15 -9, -3, +3, +9, +15 and +21 . These offset values are only exemplary and other offset values may be used, in accordance with the particular embodiment of the memory. Once the memory cells of a word line or a block are read and the LLRs determined, the technology according to the invention assigns the LLRs to the bins for each of RL1, RL2 and RL3 in a table, as shown in Tables 2 and 3 above. Linear interpolation of the LLR values between the corresponding trays (eg 0-7) is then used to determine a zero crossing point (1004) of the represented LLR values. In this regard, the LLR values in a row of the table are scanned to determine where the zero crossing point is. In consideration of Fig. 10A and Table 1 above, the zero crossing point (904) for RL1 lies between tray 5 and tray 6, which respectively have the values of LLR -38 and 5. An offset value (1006) on the X axis corresponding to the zero crossing point (1004) is selected as a calibrated offset value for the corresponding read level (e.g. RL1, RL2 or RL3). In Figure 10A, the calibrated offset value is determined to be approximately +14 tops (for example + 175mV, each peak being 25mV). In Figure 10B, the calibrated offset value is determined to be approximately +12 tops. In Figure 10C, the calibrated offset value is determined to be approximately equal to +10 tops. A calibrated offset value can be determined for each reading level (for example RL1, RL2 or RL3), as indicated above. In some embodiments, the calibrated offset values can replace the existing offset values for individual word lines or be used to adjust them, or globally for a block or one or more chips. In some embodiments, the calibrated offset voltage replaces a read level offset previously associated with an offset word line group determined by the processes 700 and / or 800, for example. In some aspects, the previously associated read level offset will be adjusted by the calibrated voltage. In such cases, it is not necessary to determine the calibrated offset voltages based on the LLR values for all the memory cells of a block, a chip or a group, but they can instead be determined based on the LLR values assigned to the bins based on a range of one or more lines of selected words, portions of a word line, one or more code words and similar. In some embodiments, the calibrated offset values may be stored in addition to the offsets determined for a group of word lines and summed at the time of a read offset operation assigned to the word line group and any offset. overall available. Reading levels can be calibrated using the above procedure at specific points during the expected life of a flash memory device. The calibration procedure can be performed, for example, when a block has been subjected to a predetermined number of programming / erasing cycles. The calibration procedure may be performed in a "heroic mode", for example in response to an error count produced in association with a read operation satisfying a predetermined error count threshold. The predetermined threshold may be defined in consideration of one or more code words, word lines, blocks, or a combination thereof, for a single read operation or for multiple read operations during a single read operation. period. In some embodiments, the predetermined threshold of errors may include failing to read or decode one or more memory cells that are the object of the read operation. For example, the error count produced may be greater than what can be managed by the ECC scheme associated with the flash memory device. In response to the identification of a word line associated with an excessively high error count (satisfying the threshold), a flash memory controller or a component thereof which implements the technology according to the present invention. the invention can read the memory cells in one or more word lines cousins of the word line identified to generate the LLR values for the respective bins, and determine a new calibrated offset value for reading the word lines using the linear interpolation process of the previous LLR. If the neighbor word lines can be read and their decoding is successful, the new calibrated offset value can then be used in an attempt to retrieve a reading of the memory cells in the identified word line. The identified word line can then be replayed using the read level set to (eg adjusted by) the calibrated offset value. Similarly, a code word (for example covering word lines or a portion of a word line) subjected to a read operation can be identified as having an error rate which satisfies a threshold for example, if all attempts to decode the code word may have failed. In response to the identification of the code word, the flash memory controller or its component implementing the technology of the invention can read the memory cells in one or more other codewords adjacent to the identified code mode. to generate the LLR values and determine the new calibrated offset value using the interpolation process of the previous LLR. If the neighboring codewords can be read and their decoding is successful, the new calibrated offset value can then be used in an attempt to retrieve the failed code word. The identified code mode can then be replayed using the read level set to (eg adjusted by) the calibrated offset value.
[0011] 0 1 2 3 4 5 6 7 RL1 -255 -108 -71 -25 -22 -70 111 146 RL2 -255 -123 -74 -24 -26 -74 109 119 RL3 191 112 70 23 -26 -74 -117 - Table 4 3033927 29 100861 Table 4 above shows the updated LLR values for each bin, after calibration of the respective reading level offsets corresponding to the LLR values of Tables 2 and 3. As can be seen from Table 4, the zero crossing point (1004) is now between bins 3 and 4 for the three read levels. Figures 10D through 10F show an example of linear interpolation graphs for recalibrating examples of read levels and / or read level offsets according to various aspects of the technology of the invention. After performing read level adjustment in accordance with the process described above in connection with FIGS. 10A-10C, the adjusted reading level (s) can then be recalibrated to verify or refine the calibration using the same process. . The resulting LLR values are assumed to eventually converge to zero offset, as indicated by Table 4 and the graphs of Figures 10D through 10F.
[0012] FIGS. 11A and 11B show examples of read level optimization modes according to various aspects of the technology according to the invention.
[0013] The architecture of the flash memory may be configured such that a subset of data contains multiple memory channels 1102, each channel 1102 containing for example one or more memory blocks 1104. Each addressable block 1104 by each Channel 1102 is further addressable by pages 1106. In the examples shown, each channel addresses a single memory block, each block comprising 256 pages (for example pages 0-255). As previously described, a page 1106 can be physically represented by a word line, so the terms page and line of words can be used interchangeably.
[0014] In some embodiments, as illustrated in Figure 11A, an offset voltage may be associated globally 1108 to all addressable blocks and pages by the memory channels. In this embodiment, the same offset value is a "global" offset used when reading the memory cells of any page or any block associated with the plurality of memory channels. Therefore, the overall offset can be calibrated using any of the techniques described herein. In some embodiments, as shown in FIG. 11B, multiple offsets 1110 may be used, with each offset value being associated with each page (word line), for example by associating each offset value with the address d. 'a page. The same offset value associated with the address of a page can be used for each page among all 3033927 memory channels. These "page offsets" can be relative to global offsets in that a global offset will be applied (and adjusted as needed) to all pages, and global offsets will be modified by the corresponding page offsets as each page is read. Figure 12 shows a flow diagram of an exemplary read level calibration process 1200 for reading a plurality of memory cells in a storage device in accordance with various aspects of the technology according to the present invention. the invention. For the purpose of explanation, the various blocks of the example process 1200 are described herein with reference to the components and / or processes described herein. The one or more blocks of the process 1200 may be implemented, for example, by one or more processors including, for example, the flash memory controller 1501 of Figure 15 or one or more components or processors of the controller 1501. In some embodiments, one or more of the blocks may be implemented separately from the other blocks and by one or more different processors or controllers. Still for the sake of explanation, the blocks of the example process 1200 are described as appearing in series, or in a linear fashion. Multiple blocks of the example process 1200 may, however, appear in parallel. Furthermore, it is not necessary that the blocks of the example process 1200 are executed in the indicated order and / or the execution of one or more of the blocks of the example process 1200 is not necessary. not necessary. According to various embodiments, the blocks of the process 1200 correspond to or complete the process described in connection with FIG. 9 and FIGS. 10A through 10F. The blocks of the process 1200, or a subset thereof, may be executed for each possible read level used in a memory device. The blocks of the process 1200 may be executed, for example, to generate, adjust and / or calibrate word lines or groups of offset word lines for RL1, RL2 and RL3. In various aspects, groups of offset word lines of different sizes and / or with different offset value matches can be generated for each different reading level. In addition, the blocks of the process 1200 can be executed to generate, adjust and / or calibrate offsets for different groups, different blocks and / or chips. The process 1200 may be implemented during the configuration of a storage device, before or during its use. In the example shown, a system according to the technology of the invention provides a reading level voltage sufficient to read a majority of the memory cells that are programmed at a predetermined programming level (1202). As previously described, the memory cells may be single-level or multi-level nonvolatile memory cells configured to be programmed at one to four programming levels. The first and fourth programming levels, for example, can be associated with first binary values (for example representative of a 0 or a binary 1 of a most significant bit) and the second and third programming levels can to be associated with the second binary values (for example, representative of a 0 or a bit of a bit of a least significant bit). As previously described, when the voltage is applied to a memory cell at a particular reading level (e.g. RL1, RL2, RL3) corresponding to the program level of the cell, the cell will drive indicating the program level. [0092] After a predetermined period in a life cycle of a memory device, reliability values corresponding to a plurality of readings of one or more of the memory cells are generated (1204). In this example, each of the readings employs a variation of the read level voltage, and each generated reliability value indicates a probability that an output state of the memory cells is equal to a predetermined programmed state, a range of values. reliability covering negative and positive values. As previously described, for the plurality of reliability values, a positive reliability value may indicate that a corresponding output state is a binary 0, and a negative reliability value may indicate that a corresponding output state is a binary 1 . After generating the reliability values, an offset voltage is identified, the offset from the reading level voltage (1206). In the illustrated examples of FIGS. 10A-10C, the offset corresponds to a zero crossing point 1004 in the range of reliability values (e.g., Tables 2 and / or 3). After identifying the offset voltage (e.g., for the read level), the read level voltage is set to a calibrated voltage based on the offset voltage (1208). According to various aspects of the technology according to the invention, the adjustment of the reading level voltage to the calibrated voltage can include, for example in association with a read operation, the recovery of the offset voltage identified with a stored location and adjusting the read level voltage by the identified offset voltage to read the memory cells. In some embodiments, the read operation is performed on the memory cells among a plurality of memory channels, each channel being configured to address one or more memory blocks. Referring to Fig. 11A, the identified offset voltage may be associated with all addressable blocks and pages by the plurality of memory channels so that the read level is adjusted by the offset voltage. identified when reading the memory cells of a page or any block associated with the plurality of memory channels. Referring to FIG. 11B, the identified offset voltage can be associated with the address of a page and the read level adjusted by the offset voltage identified when reading the memory cells associated with the address. page through any of the plurality of memory channels, each page address addressable through the plurality of memory channels being associated with a different offset voltage. In addition, the calibration process may be applied to update the offsets for the individual word lines or to update the offsets associated with optimal word line groups. A plurality of predetermined read level offsets can be stored, for example, each predetermined read level shift being associated with a group of word lines for use with a respective read level voltage when reading the read cells. memory in the group. For a respective group of word lines, the read level offset previously associated with the group can be updated with the identified offset voltage. Therefore, in association with a read operation, the updated read level offset can be retrieved from its stored location (e.g. a look-up table) to adjust the reading level voltage to the calibrated voltage and the new 25 calibrated voltage used to read the respective group of lines of words. FIG. 13 represents a process diagram of an exemplary process 1300 for calibrating reading levels for data recovery, according to various aspects of the technology according to the invention. The previous 1200 calibration process may further be applied to recover data that can not be read or decoded.
[0015] In the exemplary embodiment shown in Fig. 13, during a read operation, one or more word lines or codewords are identified as being associated with an error rate that satisfies an error threshold. (1302). Reading a 33-word line or codeword, for example, can produce a data error count that is too high to be handled by the error-correcting coding. In this regard, the read operation may not be able to read the stored data at one or more identified word lines.
[0016] 100981 In response to identifying the one or more lines of words or code words, the process 1200 of Figure 12, or one or more blocks thereof, may be invoked to retrieve data from one or several lines of words. In this regard, the memory cells in one or more word lines or codewords adjacent to the identified word line (s) or code word (s) are read to generate the plurality of reliability values described above in accordance with 10A to 10C (1304). After the reliability values are generated, the new calibrated offset voltage is identified (for example, that corresponding to a zero crossing point 1004 in the range of reliability values) and the read level voltage is adjusted / adjusted. at the new calibrated offset voltage (1306). The identified word line (s) or code word (s) are then replayed using the new calibrated read level voltage (1308). FIG. 14 represents a flow diagram of an exemplary process 1400 for regenerating a plurality of optimal offset word line groups based on the regeneration and reindexing of an error count table. according to various aspects of the technology according to the invention. For the purpose of explanation, the various blocks 20 of the example process 1400 are written here with reference to the components and / or processes described herein. The one or more blocks of the process 1400 may be implemented, for example, by one or more processors including, for example, the flash memory controller 1501 of Figure 15 or one or more components or processors of the controller 1501. In In some embodiments, one or more of the blocks may be implemented separately from the other blocks and by one or more different processors or controllers. Still for the purpose of explanation, the blocks of the example process 1400 are described as appearing in series or in a linear fashion. Multiple blocks of the 1400 process example may appear in parallel, however. Further, it is not necessary for the blocks of the process example 1400 to be executed in the indicated order and / or the execution of one or more of the blocks of the process example 1400. is not necessary. According to various embodiments, the process blocks 1400 correspond to or complement one or more blocks of the processes 700, 800, 1300 and / or 1200, and / or processes described in connection with FIG. 9 and Figures 10A-10F. Blocks of the process 1400, or a subset thereof, may be executed for each possible read level used to read the memory cells in a memory device. These memory cells are configured to be programmed at a plurality of programming levels, each programming level being determined by storing the memory cells at a respective read level voltage. The blocks of Process 1400 can be executed to generate, adjust and / or calibrate the offsets for word lines or word line groups for RL1, RL2 and RL3. A portion of the blocks of the process 1400 may be executed by the algorithm 602. In various aspects, groups of offset word lines of different sizes and / or different offset value matches may be generated for each different reading level. In addition, process blocks 1400 may be executed to generate, adjust and / or calibrate the offsets for different groups, for different blocks and / or chips. The process 1400 can be implemented during the configuration of a storage device, before or during its use. In the example shown, a system according to the technology according to the invention generates an error count table based on the reading of a first example of word lines of a memory block (1402). ). Table 400 is an example of an error count table that can be generated by the technology of the invention. As previously described, to generate a new table, each word line can be read multiple times using a read level voltage modified by a different offset voltage to produce an error count for each word line combination and respective reading level voltage. Each read can produce an error count for each offset voltage. The table is generated so that the rows of the table correspond to the word lines and the columns correspond to the offset values. The table indexes each error count produced by a corresponding word line identifier (e.g., a word line address or a partial word line address) and a respective one of the different read level voltages ( for example a read level modified by a respective offset voltage or the offset voltage). The error counts that are generated can then be indexed by word line and respective read level voltages.
[0017] In addition or alternatively, a first example of word lines of a memory block may be read, each word line being read several times using different read level voltages to produce an error count. for each word line combination and respective reading level voltage. Each line of 5 words is associated with a word line identifier (for example an address of the word line). The error count table can then be generated based on the error counts produced, the error count table indexing each error count produced by a corresponding word line identifier and a respective one of the different read level voltages used to produce the error count. [0104] In association with the configuration of a storage device implementing the technology of the invention, a plurality of optimal offset word line groups are formed (e.g., by the algorithm 602) based on the error count table and an initial division of the plurality of word lines (1404). The word line groups may be formed based on the word line identifiers used to index the error count table, each group of word lines associating a respective one of the different read level voltages with each other. a plurality of word lines on which the read operations are to be performed. As described above with respect to processes 700 and 800 and also FIGS. 7 and 8, each optimal offset line group may include a consecutively grouped portion of matched word lines with a corresponding offset voltage, with matches selected. for a global error count as low as possible for the reading of the word lines in each of the groups of offset word lines. In this regard, an error count table can be indexed by word lines and respective read level offset voltages to determine the maximum and / or minimum error counts for each of the word lines. and then the word lines organized in consecutive groups, each paired with an offset value that produces the smallest possible degradation of the error count (in comparison with the individual word lines) for the clusters.
[0018] After the generation of the optimal word line groups (including the corresponding offset voltages), the storage device is configured to perform read operations on the respective word lines of the word line groups using the voltages. of read level shifts selected for the word line groups based on the error counts in the error count table (1406). Therefore, in association with the reading of the memory cells of a particular word line of an offset word line group, the offset voltage associated with the respective shifted word line group can be identified and the memory cells read using the identified offset voltage. In various embodiments, the identified offset voltage changes the respective read level voltage to read the memory cells with fewer errors than if the respective read level voltage was not changed.
[0019] 101061 After a predetermined point in a memory block lifecycle (e.g. a point at which the memory cells in the memory block produce a bit error rate greater than a predetermined threshold or have been subjected to a predetermined number of programming / erase cycles), the optimal word line groups, including their associated offset values, can be recalibrated. In this regard, the error count table is regenerated (1408). The error count table 15 may be regenerated based on the reading of a second sample of word lines corresponding to the word line identifier used to index the error count table. For example, the error count table can be regenerated based on the replay of the plurality of word lines of a memory block, for example, under the current conditions (e.g. voltage levels). ) of the memory device.
[0020] In some embodiments, before the error count table is regenerated, the read levels and / or offset voltages used to generate the table may be calibrated. Referring briefly to Figure 13 and process 1300, reliability values corresponding to multiple readings around a respective read level voltage may be generated, a calibrated voltage for the read level voltage identified (by for example, an offset voltage for calibrating the existing read levels) and the storage device configured to read the plurality of word lines of the memory block based on the calibrated voltage in association with the read level voltage. Therefore, each of the reads can use a variation of the read level voltage and each generated reliability value can be indicative of a probability that an output state of the memory cells is equal to a predetermined programmed state ( for example the logarithm of the likelihood ratio). A range of reliability values can cover both negative and positive values. The updated offset voltage identified for rereading the word lines may correspond to a zero crossing point in the range of reliability values. [0108] The different read level voltages used to generate the initial error count table can be updated to produce updated read level voltages. Each of the different read level voltages can, for example, be adjusted by the calibrated voltage. In this regard, each of the second sample word lines is read multiple times using the updated read level voltages to produce an updated error count. The error count table can then be regenerated from the updated error counts produced. Therefore, the error count table can be updated to index each updated error count produced by a corresponding word line identifier and a respective one of the updated read level voltages. used to produce updated error counts. [0109] Once the error count table is regenerated, the optimal offset word line groups are regenerated based on the indexing of the error count table regenerated by the word lines and the error lines. read level offset voltages (1410). The optimal offset word line groups can be regenerated as described by one or more blocks of the process 700 and / or the process 800. Many of the features described above of the process examples 1200, 1300 and 1400 and related features and applications may be implemented as software processes that are specified as a set of instructions stored on a computer readable storage medium (also known as a computer readable medium) . When these instructions are executed by one or more processing units (for example one or more processors, processor cores, or other processing units), they cause the processing units to perform the actions indicated in the instructions. Examples of computer readable media include, but are not limited to, CD-ROMs, flash drives, RAMs, hard drives, EPROMs, and the like. Computer readable media do not include carrier waves or electronic signals transmitted wirelessly or over wired connections. Fig. 15 is a block diagram showing the components of an exemplary data storage system 1500 (e.g. an electronic disk) according to various embodiments of the technology according to the invention. The data storage system 1500 may include a data storage controller 1501, a storage medium 1502, and a flash memory device 1503. The controller 1501 may use the storage medium 1502 for temporary storage of data and information. used to manage the data storage system 1500. The controller 1501 may include a plurality of internal components (not shown) such as one or more processors, a read-only memory, an interface for a flash memory component (for example a multiplexer for managing the transport of instructions and data along a serial link with the flash device 1503), an I / O interface, an error correction circuit and the like. In some aspects, one or more elements of the controller 1501 may be integrated into a single chip. In other aspects, the elements may be implemented on two or more discrete components. The controller 1501, or one or more of the components contained therein, may be configured to execute code or instructions for performing the operations and functionality described herein. For example, controller 1501 may be configured to perform operations to handle flow and request address mappings and to perform calculations and generate commands. The controller processor 1501 can be used to monitor and control the operation of the components in the data storage controller 1501. The processor may be a general purpose microprocessor, a microcontroller, a digital signal processor (DSP), a circuit ASIC, an on-site programmable logic array (FPGA), a programmable logic component (PLD), a controller, a state machine, a gate logic, discrete physical components, or a combination thereof who is before. One or more instruction sequences may be stored as firmware on a ROM within the controller 1501 and / or its processor. One or more instruction sequences may be stored in software and read from the storage medium 1502, the flash memory device 1503, or received from the host device 1510 (for example, through a hardware interface). host). The ROM, the storage medium 1502, the flash memory device 1503 are examples of machine-readable or computer-readable media on which the instructions / code executable by the controller may be stored. 1501 and / or its processor. Machine-readable or computer-readable media 3033927 may generally refer to any tangible and / or non-temporary medium used to provide instructions to the controller 1501 and / or its processor, including both volatile media, such as dynamic memory used for storage medium 1502 or for buffers inside controller 1501, and nonvolatile media, such as electronic media, optical media, and magnetic media. Accordingly, the data storage system 1500 may further include a host interface 1505. The host interface 1505 is configured to be connected to a host device 1510 to receive data sent from the host device 1505. host device 1510 and send him data. The host interface 1505 may include both electrical and physical connections for the operational connection of the host device 1510 to the controller 1501. The host interface 1505 is configured to communicate data, addresses, and signals. between the host device 1510 and the controller 1501. Thus, the controller 1501 is configured to store the data received from the host device 1510 in the flash memory device 1503 in response to a write command from the of the host device 1510, and for reading the data stored in the flash memory 1503 and transferring the read data to the host device 1510 through the host interface 1505 in response to a read command from the host device 1510 The host device 1510 represents any device configured to be connected to the data storage system 1500 and to store the data in a system The host device 1510 may be a computer processing system such as a personal computer, a server, a workstation, a laptop, a PDA, a smartphone, and the like. Alternatively, the host device 1510 may be an electronic device such as a digital still camera, a digital audio player, a digital video recorder, and the like. In some aspects, the storage medium 1502 represents the volatile memory for temporary storage of data and information used for managing the data storage system 1500. In accordance with one aspect of the present invention, the storage medium storage 1502 is a random access memory (RAM) such as dual data rate (DDR) RAM. Other types of RAM may also be used to implement the storage medium 1502. The storage medium 1502 may be implemented using a single RAM module or multiple RAM modules. Although the storage medium 1502 is shown separately from the controller 1501, those skilled in the art will recognize that the storage medium 1502 may be incorporated into the controller 1501 without departing from the scope of the present invention. Alternatively, the storage medium 1502 may be a non-volatile memory such as a magnetic disk, a flash memory, a peripheral SSD, and the like. As also depicted in Figure 2, the data storage system 1500 may also include a bus. The bus may employ an appropriate interface standard, including, but not limited to, Serial Advanced Technology Attachment (SATA), Advanced Technology Attachment (ATA), and Small Computer System Interface (SCSI). small computer), Extended PCI (PCI-X), Fiber Channel (Serial Attached SCSI), SD (Secure Digital), EMMC (Embedded Multi-Media Card) embedded multimedia), UFS (Universal Flash Storage) and PCIe (Peripheral Component Interconnect Express). The host device 1510 and the data storage system 1500 may be in communication with one another via a wired or wireless connection and may be local or remote from each other. 'other. In accordance with some aspects, the data storage system 1500 may include pins (or media) for mating with a corresponding socket (or pins) on the host device 1510 to establish an electrical and physical connection. . In accordance with one or more other aspects, the data storage system 1500 includes a wireless transceiver for placing the host device 1510 and the data storage system 1500 in wireless communication with each other. The flash memory device 1503 represents a non-volatile memory device for storing the data. In accordance with one aspect of the present invention, the flash memory device 1503 includes, for example, a NAND flash memory. The flash memory device 1503 may comprise a single flash memory device or chip, and may include multiple flash memory devices or chips arranged in multiple channels. The flash memory device 1503 is not limited to any particular capacity or configuration. The number of physical blocks, for example, the number of physical pages per physical block, the number of sectors per physical page, and the size of the sectors may vary within the scope of the present invention. The flash memory may have a standardized interface specification. This standard ensures that chips from multiple manufacturers can be used interchangeably (at least to a large extent). The interface may further hide the internal work of the flash memory and return only the internally detected binary values for the data. The term "software" is intended to include, where appropriate, firmware residing in a read-only memory or applications stored on a magnetic medium that can be loaded into memory for processing by a processor. . Also, in some embodiments, multiple software aspects of the subject of the invention may be implemented as subparts of a larger program while remaining separate software aspects of the object. of the invention. In some embodiments, multiple software aspects may also be implemented as separate programs. Finally, any combination of separate programs which together implement a software aspect described herein is within the scope of the object of the invention. In some embodiments, the software programs, when installed to operate on one or more electronic systems, define one or more specific machine implementations that execute and perform the operations of the software programs. [0121] A computer program (also known as program, software, software application, script or code) may be written in any form of programming language, including compiled or interpreted languages as well as declarative or procedural languages. , and can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, object, or other unit suitable for use in an environment computer science. A computer program may, but need not, correspond to a file in a file system. A program may be stored in a portion of a file that contains other programs or data (for example, one or more scripts stored in a markup language document), a single file dedicated to the program in question, or multiple coordinated files (eg files that store 30 or more modules, subroutines or portions of code). A computer program can be deployed to run on a computer or on multiple computers that are located on a site or distributed between multiple sites and interconnected by a communication network.
[0021] It is understood that the illustrative blocks, modules, elements, components, methods and algorithms described herein may be implemented in the form of electronic hardware, computer software or combinations of both. To illustrate this interchangeability of hardware and software, various illustrative blocks, modules, elements, components, methods, and algorithms have been described above, generally in terms of their functionality. The implementation of such functionality in hardware or software form depends on the particular application and design constraints imposed on the system as a whole. Skilled craftsmen can implement the described functionality in different ways for each particular application. Various components and blocks may be arranged differently (eg arranged in a different order or partitioned in a different manner), all without departing from the scope of the present invention.
[0022] It is understood that the specific order or hierarchy of steps in the disclosed processes is presented as an illustration of some examples of approaches. Depending on the design preferences and / or other considerations, it is understood that the specific order or hierarchy of steps in the processes can be rearranged. In some embodiments, for example, some of the steps may be performed simultaneously. Therefore, the appended process claims present the elements of the various steps in an exemplary order and are not meant to be limited to the specific order or hierarchy presented.
[0023] The foregoing description is provided for the purpose of enabling anyone skilled in the art to practice the various aspects described herein. The foregoing description provides various examples of the present invention and the present invention is not limited to these examples. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other aspects. Therefore, the claims are not intended to be limited to the aspects set forth herein, but the entire scope of application is to be consistent with the language claims, the reference to an element in the singular not being intended to meaning "one and only one", unless explicitly stated, but rather "one or more". Unless otherwise specifically indicated, the term "some" refers to one or more. Male pronouns (eg, sound) include the feminine gender (eg, sa) and vice versa. The titles and subtitles that may be present are used solely for the sake of convenience and do not limit the subject of the invention. The predicative words "configured for", "can be used for" and "programmed for" do not imply any particular tangible or intangible modification of a subject, but rather are intended to be used interchangeably. A processor configured to monitor and control an operation or component, for example, may also mean that the processor is programmed to monitor and control the operation or that the processor can be used to monitor and control the operation. Similarly, a processor configured to execute code can be constructed as a processor programmed to execute the code or that can be used to execute the code. The phrases "in communication with" and "connected" mean in direct communication with or in indirect communication with one or more components, named or not named here (for example a memory card reader) [ A phrase such as an "aspect" does not imply that such an aspect is essential to the present invention or that such an aspect applies to all configurations of the present invention. Aspect-related disclosure may apply to all configurations or configurations. One aspect may provide one or more examples. A phrase such as an aspect may refer to one or more aspects and vice versa. A phrase such as an "embodiment" does not imply that such an embodiment is essential to the present invention or that such an embodiment applies to all configurations of the present invention. Implementation-related disclosure may apply to all aspects, or to one or more aspects. One implementation may provide one or more examples. A phrase such as an "embodiment" may refer to one or more implementations and vice versa. A phrase such as a "configuration" does not imply that such a configuration is essential to the present invention or that such a configuration applies to all configurations of the present invention. Configuration-related disclosure may apply to all configurations, or to one or more configurations. A configuration can provide one or more examples. A phrase such as a "configuration" can refer to one or more configurations and vice versa. 3033927 44 [01281 The word "by way of example" is used here to indicate "serving as an example or illustration". Any aspect or design described herein as "by way of example" need not be considered preferred or advantageous over other aspects or designs. 5

权利要求:
Claims (20)
[0001]
REVENDICATIONS1. A computer-implemented method, comprising: reading a first example of word lines of a memory block, each of the first word line examples being associated with a word line identifier and being read multiple times by using different read level voltages to produce an error count for each word line and respective read level voltage combination; generating an error count table based on the error counts produced, the error count table indexing each error count produced by a corresponding word line identifier and a respective voltage of the different reading level voltages used to produce the error count; and configuring a storage device to perform read operations using selected read level voltages based on the error counts of the error count table. 15
[0002]
The computer-implemented method of claim 1, wherein the storage device configuration comprises: forming a plurality of word line groups based on the word line identifiers used to index the table of words. error counts, each group of word lines associating a respective one of the different read level voltages to a plurality of word lines on which the read operations are to be performed, wherein the storage device is configured to perform a respective read operation on the respective word lines using the read level voltage of the word line group corresponding to the respective word lines.
[0003]
The computer-implemented method of claim 2, wherein the plurality of word line groups are generated based on an initial division of the word lines corresponding to the word line identifiers used to index the table of words. error counts, and wherein each group of word lines comprises a consecutively grouped portion of matched word lines matched with a corresponding read level voltage, the matches being selected for the lowest overall error count possible for the reading of the word lines in each of the groups of word lines.
[0004]
The computer implemented method of claim 2, further comprising: after a predetermined point in a life cycle of one or more blocks of memory in the storage device, regenerating the count table of errors based on reading a second sample of word lines corresponding to the word line identifiers used to index the error count table, and regenerating the plurality of word line groups based on the regenerated error count table.
[0005]
The computer-implemented method of claim 4, wherein the regeneration of the error count table comprises: generating a plurality of reliability values corresponding to a plurality of readings of the memory cells of the one or more memory blocks, each reading being performed using a different read level voltage, a range of reliability values covering negative and positive values; identifying a calibrated voltage that corresponds to a zero crossing point in the range of reliability values; and configuring the storage device to read the second sample of word lines based on the calibrated voltage.
[0006]
The computer-implemented method of claim 5, wherein the regeneration of the error count table further comprises: updating the different read level voltages based on the calibrated voltage, each of the second word line samples being read multiple times using updated read level voltages to produce an updated error count; and regenerating the error count table based on the updated error counts produced, the error count table being updated to index each updated error count produced by a user error ID. corresponding wordline and respective one of the read level voltages updated to produce the updated error counts. 3033927 47
[0007]
The computer implemented method of claim 5, wherein the predetermined point in the life cycle of the one or more memory blocks includes a point in the life cycle at which one or more readings of the memory cells in the or the multiple memory blocks produce a bit error rate higher than an error threshold.
[0008]
The computer-implemented method of claim 5, wherein the predetermined point in the life cycle of the one or more memory blocks includes a point in the life cycle at which the memory cells in the one or more blocks of memory. memory have been subjected to a predetermined number of programming / erasing cycles. 10
[0009]
A data storage system, comprising: a plurality of flash memory devices, each flash memory device comprising a plurality of memory blocks; and a controller connected to the plurality of flash memory devices, the controller being configured for, during a configuration mode: reading a first example of word lines of the flash memory devices, each of the first examples of word lines being associated a word line identifier being read multiple times using different read level voltages to produce an error count for each corresponding word line and read level voltage combination; generating an error count table based on the generated error counts, the error count table indexing each error count produced by a corresponding wordline identifier and a respective voltage of the different voltage of the error count. reading level used to produce the error count; and select reading level voltages for future read operations based on the error counts of the error count table. 30
[0010]
The data storage system of claim 9, wherein the controller is further configured for, during the configuration mode: forming a plurality of word line groups based on the word line identifiers used. for indexing the error count table, each group of word lines associating a respective one of the different read level voltages with a plurality of word lines on which the read operations are to be performed; and configuring the data storage system to perform a respective read operation on the respective word lines using the read level voltage of the word line group corresponding to the respective word lines.
[0011]
The data storage system of claim 10, wherein the plurality of word line groups are generated based on an initial division of the word lines corresponding to the word line identifiers used to index the count table. of errors, and with which each group of word lines comprises a consecutively grouped portion of matched word lines matched with a corresponding read level voltage, the matches being selected for the lowest possible overall error count for reading the word lines in each of the word line groups.
[0012]
The data storage system of claim 10, wherein associating the read level voltage with the plurality of word lines includes associating the read level voltage with a plurality of read addresses. line of words corresponding to the plurality of word lines.
[0013]
The data storage system of claim 12, wherein the controller is configured to: after a predetermined point in a life cycle of a respective memory block, regenerate the error count table based on reading a second sample of word lines corresponding to the word line identifiers used for indexing the error count table, and regenerating the plurality of word line groups based on the 30 count table; regenerated errors.
[0014]
The data storage system of claim 13, wherein the regeneration of the error count table comprises: generating a plurality of reliability values corresponding to a plurality of readings of the memory cells of the memory block; respective memory, each reading being performed using a different read level voltage, a range of reliability values covering negative and positive values; Identifying a calibrated voltage that corresponds to a zero crossing point in the range of reliability values; and configuring the storage device to read the word lines of the respective memory block based on the calibrated voltage. 10
[0015]
The data storage system of claim 13, wherein the predetermined point in the life cycle of the one or more memory blocks includes a point in the life cycle at which one or more readings of the memory cells in the one or more several memory blocks produce a bit error rate higher than an error threshold. 15
[0016]
The data storage system of claim 13, wherein the predetermined point in the life cycle of the respective memory block comprises a point in the life cycle to which the memory cells in the respective memory block have been subjected to. a predetermined number of programming / erasing cycles. 20
[0017]
A computer-implemented method, comprising: reading a first example of word lines of a flash memory device, each of the first word line examples being associated with a word line address and being read from multiple times using different read level voltages to produce an error count for each respective word line and read level voltage combination; generating an error count table based on the error counts produced, the error count table indexing each error count produced by a corresponding word line address and a respective voltage of the different 30 reading level voltages; forming a plurality of word line groups based on the error count table, each group associating a respective one of the different read level voltages to a plurality of word line addresses; and configuring a storage device to read the memory cells using a read level voltage of a generated word line group corresponding to a word line address of the memory cells to be read. 5
[0018]
The computer-implemented method of claim 17, wherein the plurality of word line groups are also generated based on an initial division of the word lines corresponding to the word line addresses used to index the table of words. error counts, and wherein each group of word lines includes a consecutively grouped portion of matched word line addresses with a corresponding read level voltage, the matches being selected for the lowest overall error count possible for the reading of the word lines in each of the groups of word lines.
[0019]
19. The computer-implemented method of claim 18, further comprising: after a predetermined point in a life cycle of one or more memory blocks, regenerating the error count table based on reading a second sample of word lines corresponding to the word line identifiers used to index the error count table, and regenerating the plurality of word line groups based on the count table of 'regenerated errors.
[0020]
20. The computer-implemented method of claim 19, wherein the predetermined point in the life cycle of the one or more memory blocks includes memory cells in the one or more memory blocks that have been subjected to a number of memory blocks. predetermined cycles of programming / erasure.

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申请号 | 申请日 | 专利标题

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US14/664,768|US9720754B2|2014-11-20|2015-03-20|Read level grouping for increased flash performance|

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US14664768|2015-03-20|

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